FPGA Acceleration of Sparse Matrix-Vector Multiplication Based on Network-on-Chip (bibtex)

by H.-Y. Jheng, C.-C. Sun, S.-J. Ruan, J. Götze

Reference:

H.-Y. Jheng, C.-C. Sun, S.-J. Ruan, J. Götze, FPGA Acceleration of Sparse Matrix-Vector Multiplication Based on Network-on-Chip, In 9th European Signal Processing Conference (EUSIPCO-2011), Barcelona, Spain, 2011.

Bibtex Entry:

@Conference{Jheng2011, Title = {FPGA Acceleration of Sparse Matrix-Vector Multiplication Based on Network-on-Chip}, Author = {H.-Y. Jheng and C.-C. Sun and S.-J. Ruan and J. G\"otze}, Booktitle = {9th European Signal Processing Conference (EUSIPCO-2011)}, Year = {2011}, Address = {Barcelona, Spain}, Month = {August} }

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